Low speed phaselock speed control system

ABSTRACT

A motor speed control system for an electronically commutated brushless D.C. motor is provided which includes a phaselock loop with bi-directional torque control for locking the frequency output of a high density encoder, responsive to actual speed conditions, to a reference frequency signal, corresponding to the desired speed. The system includes a phase comparator, which produces an output in accordance with the difference in phase between the reference and encoder frequency signals, and an integrator-digital-to-analog converter unit, which converts the comparator output into an analog error signal voltage. Compensation circuitry, including a biasing means therein, is provided to convert the analog error signal voltage to a bidirectional error signal voltage which is utilized by an absolute value amplifier, rotational decoder, power amplifier-commutators, and an arrangement of commutation circuitry, forming an integral part of the phaselock loop and including position decoders, switches, and rotor position sensors, all cooperating to control the acceleration and deceleration of the motor to achieve symmetrical bi-directional torque control thereof. The phase comparator and integrator-digital-to-analog converter unit cooperate with a simplified overspeed control circuit to derive a signal which is utilized in the system to get the motor at its desired speed and to thereafter maintain it at that speed.

Fulcher et al.

[ LOW SPEED PHASELOCK SPEED CONTROL SYSTEM [75] Inventors: Robert W.Fulcher, College Park;

John Sudey, Timonium, both of Md.

[73] Assignee: The United States of America as represented by theNational Aeronautics and Space Administration Office of GeneralCounsel-Code GP, Washington. DC.

[22] Filed: Sept. 27. 1973 [21] App]. No.: 401,466

52] US. Cl. 318/314; 318/318; 3l8/34l {Sl Int. Cl. H02p 5/00 [58 Fieldof Search u. 3l8/l38, 254, 3l4. 3l8,

[56] References Cited UNITED STATES PATENTS 3,68 l .670 8/l972 Kadokura3 I 8/3 I 8 3.753.067 8/l973 Milligan .3l8/3l4 3,7(14 888 lU/l973Anderson l. 3l8/3l8 3,781.15) H1974 Malkiel 3l8/254 Primary Exuminew-U.Zw Rubinson Attorney. Agent, or Firm-R. F. Kempf; John R. Manning May13, 1975 [57] ABSTRACT A motor speed control system for anelectronically commutated brushless DC. motor is provided which includesa phaselock loop with bi-directional torque control for locking thefrequency output of a high density encoder. responsive to actual speedconditions, to a reference frequency signal, corresponding to thedesired speed. The system includes a phase comparator, which produces anoutput in accordance with the difference in phase between the referenceand encoder frequency signals, and an integrator digital-to-analogconverter unit, which converts the comparator output into an analogerror signal voltage. Compensation circuitry, including a biasing meanstherein, is provided to convert the analog error signal voltage to abi-directional error signal voltage which is utilized by an absolutevalue amplifier. rotational decoder, power amplifier-commutators. and anarrangement of commutation circuitry, forming an integral part of thephaselock loop and including position decoders, switches, and rotorposition sensors, all cooperatingto control the acceleration anddeceleration of the motor to achieve symmetrical iii-directional torquecontrol thereof. The phase comparator and integrator-digital-to-analogconverter unit cooperate with a simplified overspeed control circuit toderive a signal which is utilized in the system to get the motor at itsdesired speed and to thereafter maintain it at that speed.

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PHASE CURRENT ANALOG COMP l8 SOURCE ERROR OUT BI-DIRECTIONAL ERRORSIGNAL 7 POLARITY DETECTED Fm m m 1 LOW SPEED PHASELOCK SPEED CONTROLSYSTEM ORIGIN OF THE INVENTION The invention described herein was madeby employees of the United States Government and may be manul'acturedand used by or for the Government for governmental purposes without thepayment of any royalties thereon on or therefore.

FIELD OF THE INVENTION The invention relates to motor speed controlsystems and. more particularly. to a phaselock servo system for anelectronically commutated brushless DC motor capable of operating atextremely low speed and having bi-directional torque control.

BACKGROUND OF THE INVENTION There are. of course. a large number ofdifferent types of motor speed control systems presently in use which.in general. adequately serve the functions for which they are designed.However. conventional systems do. generally speaking. suffer certaindisadvantagcs. particularly in specified areas such as compatabilitywith low motor speed operation and ability to provide stable operationover extended speed ranges. Further. many olthesc systems are overlycomplex and thus excessively expensive to build and maintain as well asbeing incompatible with spacecraft applications. Moreover. systemscomparable to that of the invention customarily require an externaldigital clock (in addition to a reference input) and are not compatiblewith conventional analog servo compensation. A further dis advantageotprior art systems is that they are generally only applicable to A.C.or brush-type DC. motors. with such motors generally having theattendant disadvan tages described below. Also. many of these systems donot provide bi-directional torque control. Further. although overspccdcontrols have been incorporated in such systems. in may instances. thishas been done through the use of a rather complex design. It is alsonoted that typical prior art systems employ low pass filters to achieveconversion of a digital or pulse-width error signal into an analog errorsignal and this ap proach presents problems. particularly where employedto achieve wide servo bandwidth. For example. such an approachintroduces excessive phase lag into the control loop and actually limitsthe gain and band width which can be achieved. Finally. thecharacteristics provided by many prior art systems involve limitcycling. hunting. or excessive jitter. all of which limit precise lowspeed operation and hence suffer obvious attendant disadvantages.

SUMMARY OF THE INVENTION In accordance with the invention. a motor speedcon trol system is provided which either overcomes or substantiallyreduces the effects of the disadvantages of the prior art. For example.the system of the invention is sell locking and provides both adjustablegain and adjustable DC. bias. Considering these latter two features morespecifically. the invention provides for selection of the relationshipbetween the changes in the input pulse duration times and changes in theoutput analog error \oltage and also for setting of the output level ofan integratondigital-to-analog converter unit to vary about any desiredDC. level. This latter feature. which (ill is important becausemechanical motor loads can often be separated into fixed and variablecomponents, permits the phase locked loop described herein below tooperate at any desired percentage of pulse width. In addition. theoutput signal is compatible with conventional analog servo compensation.and the converting techniques used is compatible with low speed directdrive torquer operation. such as 3 rpm with a l6.384 cycles perrevolution encoder. In this regard. the system enables stable operationover a speed range of about 2 to I00 rpm and provides both high gain andwide bandwidth servo operation at low speeds. All this judiciouslytailored with bi-directional poweramplifier commutation to removepositive as well as negative torque disturbances.

Further. the use of an electronically commutated brushless DC. motorwith the speed control system provides a number of advantages ascompared with systems which use AC. motors (cg. reduced weight andpower) and brush-type DC. motors (e.g.. advantages such as no brushproblems. low RFl/EMI characteristics and compatibility with spacecraftenvironments). In addition. the system incorporates overspced control ina highly simplified manner. and. as will become more apparent. providesa smooth transition from an out-of- Iocl: condition to the phasclockmode. Other advantages include the elimination of the effect of motorelectrical time constant by viewing the motor as a torque transducerand. as a consequence. controlling motor speed by controlling current tothe motor windings in contrast to applied voltage. Further. theelimination of low pass filters. in converting the pulse width errorsignal into a corresponding analog signal. provides significantimprovement in system responsiveness and stability and is particularlyimportant in applications such as in driving a tape recorder because ofdecreased flutter. The system of the invention produces an error signalwhich corresponds exactly to the continuous waveform at the samplinginstant. In addition. the pulse width frequency (carrier) is removedand. as stated. only small discontinuities between one amplitude and thenext remain. thereby resulting in a relatively smooth torquecharacteristic and low jitter.

Considering the invention itself in more detail. a motor control systemfor a brushless. electronically commutatcd DC. motor is provided whichemploys phasclock techniques to provide extremely accurate speedcontrol. In accordance with a presently preferred embodiment. the motorspeed control system comprises a reference frequency oscillator forgenerating a signal having a frequency proportional to the desired speedof the brushless DC. motor; a high density encoder responsive to actualmotor speed for generating an output having a frequency proportional tothat speed; a phase comparator for comparing the frequency of thereference frequency oscillator output with that of the encoder outputand generating a pulse output in accordance therewith; anintegrator-digitalto-analog converter unit for converting the phasecomparator output into an analog error signal voltage; a compensationnetwork for converting the analog error signal to a bidircctional errorsignal which is combined with the output of a simplified overspeedcontrol circuit so that the system achieves both phaselock and overspeedcontrol; and means for utilizing the bidirectional crror signal tocontrol the acceleration and deceleration of the motor to obtain thesymmetrical bimutation means is an integral part of the phaselock loop.

Other features and advantags of the invention will be set forth in or beapparent from the detailed description of a presently preferredembodiment found hereinbelow.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a block diagram of a motorspeed control system according to a presently preferred embodiment ofthe invention;

FIGS. 2(a) to 2(m) are voltage waveform diagrams for the voltages atvarious points in the system of FIG. I (and the circuits of FIG. 3 and4);

FIG. 3 is a schematic circuit diagram, partially in block form. showingthe circuit details of the phase comparator and ovcrspced circuit ofFIG. 1;

FIG. 4 is a schematic circuit diagram, largely in block form, of theintegrator-digital-to-analog converter unit of FIG. I; and

FIG. 5(a) to 5(1') are voltage waveform diagrams used in explaining theoperation of bi-directional control of FIG. I.

DESCRIPTION OF A PREFERRED EMBODIMENT Referring to FIG. I, there isshown a block diagram of the invCntive motor speed control systemadaptable to a tape recorder or more specifically to a helical taperecorder. Although the invention is described relative to driving a taperecorder. it will of course be understood that it has widerapplicability. particularly with motor driven systems where precisecontrol thereof is desired. The system includes a reference frequencyoscillator which is considered to be external to the control systemproper, and the reference frequency provided thereby can be derived, inan exemplary embodiment, from the time reference provided in thespacecraft in which the system is incorporated. The reference frequencyoscillator I0 governs the long term speed stability of the controlsystem since, as explained hereinbelow, the control system locks thefrequency of the signal of high density encoder 20 to that of thereference output provided by oscillator 10. The reference frequencychosen is a function of the speed (in revolutions per second) desiredand the encoder density (in lines per revolution), and an exemplaryfrequency of H.760 Hz may be used in the specific embodiment underconsideration. Further. a square wave of approximately voltszero-to-pcak is desirable for the specific application underconsideration.

The output of reference oscillator is connected to a frequency divider12 which is considered an integral part of the control system. Thedivider I2 includes logic circuits for dividing the l4.760 Hz referencefrequency by a factor of I8. A switch 14 permits selection of the 14.760Hz of oscillator 10 for playback or the 820 Hz frequency of divider 12for recording. The output of switch 14 is connected to a first pulseshaper I6 which can be a conventional monostable multivibrator,

the output of pulse shaper I6 forming one input to a phase comparator 18described hereinbelow.

The second input to phase comparator I8 is derived from high desityencoder 20. The encoder 20, as indicated in FIG. I, is part of anintegral assembly which also includes DC. motor 22, indicated in dashedlines, and a tape/head load 24. In an exemplary embodiment, the encoder20 takes the form of a conventional photo optical encoder or inductosyn"and produces l6,384 cycles per revolution to establish a servo referenceof 820 Hz and 14,760 Hz, respectively, for 3 rpm and 54 rpm operation ofmotor 22.

The accuracy of encoder 20 is extremely important in that the totalsystem performance only be as good as the encoder itself. A number ofproblems are encoun' tered in providing this accuracy such as lineresolution and detection limitations. Best results are achieved by usinga high density encoder (anyone of the high desity precision designsbeing suitable) which minimizes both phase shift in the forward loop (anacute problem at the 820 Hz reference frequency) and the effects ofdisturbing torques. As presently used, however, it must have at least16,384 counts per revolution in order to be compatible with stable,relatively high bandwidth servo operation as low as 2 rpm. With the useof higher desity encoders. the control system will pass more encodererror haromics which give rise to higher speed jitter. In particularapplication for which the invention is used, this can be tolerated. Forother applications it may be desirable that the phase comparator I8(discussed in detail hereinafter) be modified so as to code the outputthereof into yet another (set-clear) binary or trilevel sequence withappropriate filtering being used to recover the error signal. Further,the encoder could include parallel readout stations which would be usedone at a time. the other station being automatically switched in if thefirst falls.

The output of encoder 20, generally a sine wave signal having anamplitude of about 4 volts peak-to-peak with inherent amplitudemodulation caused by mechanical imperfections, is coupled to amplifierlimiter 26 which converts the sine wave to a square wave such thaterrors due to amplitude modulation are reduced. The amplifier limiter 26can take a number of forms and can. for example, utilize conventionalzero crossing techniques to produce the desired square wave output.Limiter 26 preferably produces a square wave output of approximately 5volts zero-to-peak. The output of limiter 26 is connected to a secondpulse shaper 28 (identical to pulse shaper 16) which is in turnconnected to phase comparator I8. Pulse shapers l6 and 28 both convertthe square wave inputs thereto into very narrow pulses as indicated bythe waveforms V U) and V U), respectively, in FIG. I and FIGS. 2(a) and2th). Each of the pulse shapers I6, 28 preferably comprises a monostablemultivibrator adjusted to provide an output pulse of approximately 06micro second at the half voltage point.

Phase comparator 18 provides a digital error signal in the form ofvariable duty cycle rectangular waves, with each of the rising orleading edges thereof occurring at a V U) pulse and each of the fallingor trailing edges occurring at a V,-,;(I) pulse, thereby achievingpulses having a pulse width depending upon the relative phase of V U)and vp|j(f). System load disturbances will cause instantaneous angularposition error or phase error between vivid!) and V U) which modulatesthe relative location of the trailing edges of the digital error signal,thereby effecting variation in the signal duty cycle or pulse widths.

Referring to FIG. 3, there is shown a block diagram of a simple phasecomparator, corresponding to comparator 18 together with an associatedoverspeed protection circuit 30, integrator-D/A converter unit 44,compensation network 46, and operational amplifier 80 (including inputresistors 48 and 50 and feedback resistor 52], all these components alsobeing shown in FIG. I. As illustrated, comparator overspecd protectioncircuitry 18, 30 includes set"clear" flip-flop 34, NAND gate 36, bufferamplifier inverter 38 and RC network 40, all interconnected shown inFIG. 3. More particularly, the set input 31 of flip-flop 32 is connectedto receive the V U) output of pulse shaper 16 whereas the clear input 33in connected to receive the V -(I) output of pulse shaper 28. Asillustrated, the Q output of flip-flop 32 is connected back to the setinput 31, and the G output is similarly connected back to the clearinput 33. The Q output of flip-flop 32 is also connected to two inputsof integrator-D/A converter unit 44 which has its output applied viacompensation network 46 to input resistor 50 of operational amplifier80.

A typical unit for phase comparator 18, including flip-flop 32 and itsset input 31 and clear input 33, is a Diode-Transistor Micrologic PulseTriggered Binary Gated Flip-Flop (DTuL 950) supplied by Fairchild Cameraand Instrument Corporation and operating as a R-S Flip-Flop or CounterStage. The details of this flip'flop and its operation are disclosed inFairchild data sheet SL-IO dated August 1965.

Respecting overspeed protection circuitry 30, the operation of whichwill be discussed in detail hereinafter, one input 35. of flip-flop 34is connected to pulse shaper l6, and the corresponding output Q is connected back to input 35 as well as to input resistor 48 of operationamplifier 80 via amplifier inverter 38 and RC network 40. Another inputto flip-flop 34 is direct input 37 which is connected to and receivesthe output of NAND gate 36, the inputs of which are from the 6 output offlip-flop 32 and pulse shaper 28.

The details of the makeup of integrator-D/A converter unit 44 are shownin FIG. 4. As illustrated, the integrator-D/A converter unit 44 includesan input amplifier 53 which receives the Q output of phase comparator18, this output also being connected to a first monostable multivibrator56. The output of amplifier 53 is connected to a constant current source60, the output of which is applied to one end of a first capacitor 62,the other end thereof being grounded. The signal developed acrosscapacitor 62 is coupled to the input of buffer amplifier 64 which alsohas a variable reference voltage E connected thereto via switch 65. Theoutput of buffer amplifier 64 is connected to an FET. switch 66 whichreceives a control input from monostable multivibrator 56. Monostablemultibibrator 56 is also connected to a second monostable multivibrator68, the output of which is connected to a dump circuit (clamp) 70 havinga ground terminal and an input connected from capacitor 62. The outputof FET. switch 66 is connected to ground through a second capacitor 72and to a final buffer amplifier stage 74 which has. at its output. ananalog error signal.

Monostable multivibrators 56 and 68 and buffer amplifiers 64 and 74 canbe commercially available micm" circuits. The remaining circuits are ofconventional construction. Except for RC networks (not shown), which areused to set the pulse width durations -of the monostable multivibrators56 and 68, no differentiators and filters are required for themicro-circuit version.

The function of integrator-BIA converter unit 44 is to translate thepulse width information contained in the output of phase comparator 18into a corresponding analog signal. The narrow input reference pulses VU) and encoder pulses V U), derived from pulse shapers I6 and 28 andshown in FIGS. 2(a) and (11), respectively, provide setting and clearingof flip-flop 32 of comparator 18, resulting therefrom in an outputwaveform V9 (r), shown in FIG. 2(c), which is applied to both amplifier53 of integrator-D/A converter unit 44 is amplified and thereafterapplied to constant current source 60 which provides a signal forcharging first capacitor 62 during the positive going portion of a pulseof the amplified V (r) waveform, the charging of capacitor 62terminating at the end of the positive portion of the duty cycle ortrailing edge of the pulse of the amplified V (I) waveform. Asillustrated in FIG. 20), V A!) is the voltage waveform developed acrosscapacitor 62. Thus, capacitor 62 serves as a square wave integrator forthe total duration of the positive pulses (compare FIG. 2(c] and 20)).The integration operation performed by capcitor 62 is terminated at thetrailing edge of each input pulse of waveform V (1). The integratedsignal, developed across capacitor 62, is coupled to FET. switch 66 viabuffer amplifier 64 which has its bias set by reference voltage E,,.,.

It will be noted that the DC. bias of the digital-toanalog converter 44can be set to vary about any desired D.C. level by varying the referencevoltage E connected between buffer amplifier 64 and ground via switch65. This feature is important in motor control applications becausemechanical loads can often be separated into fixed and variablecomponents. In addition, this control also permits the phaselock loop tooperate at any selected percentage pulse-width.

At the same time as the integration operation is oc curring, thetrailing edge of the corresponding pulse of waveform V (t), as appliedto monostable multivibrator 56, is used to trigger monostablemultivibrator 56. Multivibrator 56 produces an output pulse (seewaveform V U) of FIG. 2(d)) which *closes" FET. switch 66 for a timet,,, determined by the pulse width of the output pulse of multivibrator56, and second capacitor 72 charges to a value corresponding to theamplitude of the pulse being applied thereto from FET. switch 66. Thus.any change in the pulse width of the input pulses of waveform V (1) tointegrator-D/A converter unit 44 is reflected by a corresponding changein the voltage level on capacitor 72 for each pulse cycle.

To prepare the integrator-D/A converter unit 44 for each succeedinginput pulse of waveform V (1), the output of multivibrator 56 isprocessed to produce a pulse having a leading edge which corresponds tothe trailing edge ofthe output pulse of multivibrator 56. To this end,the output from multivibrator 56 (see waveform V (t) of FIG. 2(d)) isapplied to multivibrator 68 whose output (see waveform V U) of FIG.2(e)) is coupled to dump circuit 70 which provides a low impedance pathin parallel with capacitor 62 for the discharge thereof for a time 1Hence, with the aid of dump or clamp circuit 70 there is provided ameans for discharging capacitor 62 so that it will be in the dischargedcondition when a succeeding pulse is applied thereto from constantcurrent source 60, which succeeding pulse charges capacitor 62 asdescribed above. Amplifiers 64 and 74 are connected as voltage followersand hence serve as buffer stages presenting high input impedanccs to thecapacitor charing circuits of 62 and 72, respectively.

The switching process described above is repeated within the period T(one half of this time being equal to the delay time of theintegrator-D/A converter 44 unit), and the output is the staircasewaveform V,,,,,(t) shown in FIG. 2(l'l when the input V (1) waveform isphase modulated.

Since the control system described herein involves position detectingand is one which controls the instantaneous phase of a rotating torquemotor, the system is inherently unstable. Accordingly, error ratedamping is required along with integral compensation to reduce thesteady state error. To this end, compensation network 46, connected toreceive the analog error signal (V U) waveform of FIG. 2(1)) fromintegrator-D/A converter unit 44, includes error rate damping andinctrgrating networks (not shown), While it is essen tially a frequencysensitive circuit used to adjust the gain and phase of the error signalfrom integrator-D/A converter unit 44 to optimize system performance, italso includes an amplifier inverter stage 45 having a biasing means forestablishing the Zero level of a bidirectional error signal therefrom.

The output of compensation network 46 is connected to resistor 50 ofoperational amplifier 80, operational amplifcr 80, as shown in FIG. 3,including suitable input resistors 48 and 50 and a feedback resistor 52.As will be discussed in more detail hereinafter, overspeed controlcircuit 30 is coupled to resistor 48 of operation amplifier 80 whichfunctions to essentially combine the bi-directional error signal toessentially combine the bi-directional error signal with the output fromover speed circuit 30.

The comparator-over-speed circuit 18,30, along with integrator-D/Aconverter unit 44, compensation networks 46, and operational amplifier80, enables the motor speed control system to perform three functionalmodes of operation, namely: l start and acceleration condition, (2)phaselock and (3) ovcrspecd control and deceleration condition. Beforeproceeding further, the general details of these three functional modesof operation will be presented.

The first function mode, referred to as the start (underspeed)condition, is performed by flip-flop 32 and its associated controlcircuitry, integratorD/A con verter unit 44, compensation network 46,and operational amplifier 80 with its resistors 50 and 52. Initially,when power is applied to the motor speed control system, there is nooutput from high density encoder 20. Since reference frequencyoscillator is operational, a reference pulse stream V U) is immediatelyapplied from pulse shaper 16 to set input 31 of flip-flop 32 of phasecomparator 18, thereby setting flip-flop 32, and therefore the Q outputthereof, to a one or more precisely in the example chosen to 5 voltszero-to-peak state. This output signal is furnished to integrator-D/Aconverter unit 44, where it is integrated until saturation is reached.and thereafter fed through the remaining circuitry of the phaselockloop, including the commutation network of brushless DC. motor 22, aswill be described in detail hereinafter, at a precise amplitude to theappropriate winding of motor 22.

Immediately, the rotor (not shown) of motor 22 starts rotating withincreasing velocity, i.e., it acclcr ates. Since encoder 20 is coupledto the rotor by output shaft 92 of motor 22 (see FIG. I), the pulserepetition rate of the pulses from encoder 20, and ultimately from pulseshaper 28, increases to approach that from pulse shaper 16, at whichtime, the motor 20 will be operating at its desired speed. Moreparticularly, as the pulses from pulse shaper 28 increase in pulserepetition rate to approach that from pulse shaper 16, the accelerationof the motor tends to decrease and finally approaches zero (motor 22 ata constant average velocity) when the pulses from the two pulse shapers16, 28 are at the same pulse repetition rate, this being due to theoperation of flip-flop 32 in accordance with the clear and set inputs 33and 31 thereof.

It is at this point that the system starts to operate in its phaselockmode. Flip-flop 32 is set by V H) from pulse shaper l6 and cleared by V1!) from pulse shaper 28, pulse by pulse, establishing alternate wave ofthe same pulse repetition frequency as the reference pulses but ofvariable duty cycle in accordance with the pulses from pulse shaper 28.The duty cycle of this rectangular wave is proportional to the phaseerror, within a linear operating range of i 1r radians with respect tothe frequency of the reference signal where a percent cycle (squarewave) corresponds to zero phase error in the situation where the controlsystem is so set to provide maximum control thereby. Accordingly, shouldmotor 22 start to slow down, phase comparator 18 provides at its outputa pulse type signal in which the duty cycle of the individual pulses,related to the motor speed, is utilized through circuitry, to bedescribed in detail hereinafter, to bring motor 22 back to proper speed.

As long as the system is in mode 1 or 2, start and accelerationcondition and phaselock condition, respectively, ovcrspecd circuit 30has no influence on the sys tem. More particularly, by action of NANDgate 36 (see waveform output V in FIG. 2(hl) and the feedback from O toinput 35 of flip-flop 34, the 6 output of flip-flop 34 is maintained at5 volts zero-topeak (see waveform V ,(r) in FIG. 2(i')). This 5 volts iscoupled to buffer amplifier inverter 38, which preforms the logicfunction of providing zero volts output (see waveform V in FIG. 2(j))for a predetermined positive input voltage, which in this case is 5volts. Accordingly, the output from ovcrspecd circuit 30 (see waveformoutput V U) in FIG. 2(kl) applied to resistor 48 of operationalamplifier is 0 volts and has no influence on the system.

The ovcrspecd mode, utilizing ovcrspecd circuit 30, comes into play onlyat such times as motor 22 exceeds its desired speed, for example, wheretwo consecutive Vr-fl pulses occur without an intervening V U) pulse. Asshown in FIG. 3, NAND gate 36 and flip-flop 34 cooperate in detectingwhen the frequency of the signal from encoder 20 is greater than thatprovided by the signal from reference oscillator 10 (or frequencydivider 12). More particularly, with motor 22 in this condition, NANDgate 36 has applied thereto (note ovcrspecd portion of the waveform ofFIG. 2] two positive signals of 5 volts zero-to-pcak, one from pulseshaper 28 (Vr lr) waveform of FIG. 2(b)) and the other from the 6:12output of flip-flop 32 (T (1) waveform of FIG. 2(gl). It thereforeprovides to input 37 of flip-flop 34 zero volts or a logical zero levelfor the pulse duration of its output (see waveform V 4!) in FIG. 2(Ii)).With zero volts at input 37, flip-flop 34 function such that 6, is atzero volts or logical zero level (see waveform V .0) in FIG. 2(1))regardless of what signal is applied to input 35. Buffer amplifierinverter 38 thereafter provides volts zeroto-peak output for the periodof time beginning with the occurrence of the second V -(I) pulse andending with the occurrence of a V U) pulse. (see waveform V ,.(l) inFIG. 2(j)l which is in turn coupled to resistor 48 of operationalamplifier 80 via RC network 40.

RC network 40. whose output voltage V.. (i) takes the waveform shown inH6. 2(k). prevents any noise signal from entering operational amplifier80 from ovcrspeed circuit which could influence phaselock operation. Inother words. RC network 40 only allows a signal to be coupled tooperational amplifier 80 from ovcrspccd circuit 30 when motor 22 istruly in over speed condition (operational amplifier output V,..,(r)).

Accordingly, by the operation just described. it is only when motor 22exceeds its desired speed that a positive signal is applied to resistor48 of operational amplifier 80 from overspeed circuit 30 which in turnsubstracts from the signal at resistor 50 of operational amplifier 80.thereby Causing a negative acceleration (deceleration) of motor 22.

The function of the first and third operational mode just discussedmight be said to be of the so-called "bangbang type. each operationalmode being unsta ble in nature until motor 22 reaches its synchronousspeed. When the motor 22 reaches the phaselock condition. synchronousspeed. and the system is functioning in its second operational mode. theoutput of flipflop 32 is a rectangular wave whose duty cycle is afunction of the relative phase of the inputs from pulse shapcrs l6 and28.

Referring again to FIG. 1. the bi-directional control feature of theinvention will now be considered with the system operating in the phaselock mode. Operational amplifier is connected to an absolute valueamplifier (AVA) 82. which is arranged and designed to accept. amplify,and rectify. cg, a bi-directional error input signal V, (shown in FIG.5(a)) from operational amplificr 80. The bi-directional error input.while shown as a smooth curve in FIG. 5(a). is in fact composed ofwaveform Vmill) of FIG. 2(m). waveform V,..,(t). as shown. being only asmall portion of waveform V U) at the peak negative excursion N,;thereof. AVA 82 re ceivcs this bi-dircctional error input V, (r) anddevelopes corresponding outputs-rectified error signals, ul and polaritydetection signal. V,,(t). (sec FIGS. 5th) and Sit). respectively]. thelater signal being developed with the cooperation of rotation decoder 84at the output thereof. the input thereto being front AVA 82. Rotationaldecoder 84 also controls clockwise (CW) and counterclockwise (CCW)operation of motor 22. as commanded. Commands for the selection of themotor operating direction are effected through CW and ((Vl' controlinputs. indicated by arrows 84A and 848. being applied to rotationdecoder 84. as for example. transistor transistor logic. TTL. lcvclsignals.

Rotation decoder 84 is connected to a pair of position dccodcrs 8b towhich it applies polarity detection signal. \,.t. l of Flti. 5(C), Alsoconnected to the position decoders 86 are respective ones of positionsensors 88 which produce signals related to the position of thepermanent magnet rotor (not shown) of motor 22.

The rectified error signals, V -(t) of FIG. Sb. from AVA 82 are appliedto two identical power amplifiereommutators 42. each including anoperational amplifier 42A. to which a respective rectified error signal.V.\-(t). from AVA 82 is applied. and electronic power commutator 423. towhich the output signal from its associated position decoder 86 isapplied. The output signal from amplifier 42A is coupled to powercommutator 423. To minimize lags occurring in the phaselock controloperational mode. current feedback is provided. in each case. from theoutput of power commutator 42B to the input of amplifier 42A. in such away that the electrical time constant of motor 22 does not influenceopen loop response at crossover. Power commutators 428, under thecontrol of position decoders 86 and with the aid of suitable logic gates(not shown). use the outputs of rotar position sensors 88 to switch thestator windings 22A. 22B via switches 90 so as to apply to the statorwinding 22A. 22B. at the proper time. the output signals from powercommutators 428 to provide commutation and therefor continuous rotationof the rotor of motor 22.

Each of the power amplifier-commutators 42. just discussed. isfundamentally a straight-forward amplifier which operates. as previouslydescribed. in conjunction with respective ones of position sensors 88.respective position decoder 86. and rotational decoder 84. However.power amplifier-commutators 42 utilizes two features which make themunique. The first is the provision of current feedback which effectivelymakes the operational amplifiers 42A current sources. thereby moving theelectrical time constant to a very high frequency which is well beyondthe control loop frequency making the control essentially insensitive tomotor back E.M.F.. The other feature is the bi directional capabilityprovided.

Motor 22 is shown as a double delta brushless DC. motor which comprisesa permanent magnet rotor (not shown) and two wound stator windings 22Aand 22B separated by 30 electrical degress. each comprising threenon-rotating windings connected in a delta configuration. Statorwindings 22A. 22B are interconnected via respective one of two sets ofsix solid state switches 90namely. switches 90A. 90B. 90C. 90D. 90E and90F for winding 22A and switched 90G. 90H. 90L 90]. 90K and 90L forwinding 22B-with respec' tive power commutators 42B. They are energized.as previously mentioned. in accordance with signals from the respectivepower commutators 428 being applied thereto via cooperating switches 90under the control of respective position decoders 86. Hence. motor 22 iscomparable to a brush DC. motor with twelve commutators bars perelectrical cycle.

While not shown, motor 22 is provided with a slotted disc whichinterrupts. in sequence. six light beams (not shown) associated withposition sensors 88. Moreover. although. in the embodiment underconsideration. the rotor position is sensed optically by light emittersand phototransistors. other techniques such as Hall effect devices.magneto-resistors and even auxiliary stator windings can also be used.Since brushlcss motors and their associated commutation circuitsresponsive to such sensors are well known, a detailed descriptionthereof will be omitted. It is important to note here that thecommutation circuits for brushless DC. motor 22 form an integral part ofthe phaselock loop. particularly in their novel inconnections andcooperation. as de' scribed hereinabove, with rotational decoder 84 andpower amplifier-commutators 42.

The use of two delta stator windings 22A. 22B separated by electricaldegrees and connected in parallel overcomes the low speed operationallimitations of motor 22 by reducing the torque ripple often found in DC.brushless motors. Each delta winding 22A, 22B of motor 22 commutateswithin a 60 electrical degree zone. generally resulting in relativetorque sensitivity and back E.M.F. variations from 0.866 to unity.However. because each delta winding is separated by 30 electricaldegrees, the actual relative torque and back E.M.F. variations canceland vary only from 0.94 to unity. Further, the double delta motorwinding scheme has inherent reliability in that there is no single pointfailure (short or open) in one delta windings drive that preventsphaselock operation with the other delta winding.

It should be noted that the requirement for bidirectional torques is notto enable motor 22 to be commanded in CW and CCW directions since thiscan be done merely by reversing the motor commutation sequence, butrather so that either positive or negative torque disturbances are keptunder symmetrical servo control. cg. the motor can also be controlled inthose tape recorder systems wherein the tape itself, in some instances,drives the motor. This consideration includes both long term andinstantaneous loads.

Referring again to FIG. 1. the rotor of motor 22 is provided with outputshaft 92 which serves to drive tape head load 24 or other conventionalmechanical loads which require precision drives. Output shaft 92 is alsoconnected to encoder 20 and to the slotted disc (not shown). mentionedabove as cooperating with position sensors 88.

Although the invention has been described with respect to an exemplaryembodiment thereof. it will be understood that variations andmodifications can be effected in this exemplary embodiment withoutdeparting from the scope and spirit of the invention. For example, whilein the exemplary embodiment position sensors 88 and high density encoder20 are illustrated as being two independent units connected to outputshaft 92, they can of course be combined in a single unit.

What is claimed is:

1. In combination. a brushless DC. motor and motor speed control systemfor controlling the speed of said motor. said system comprising:

means for generating a reference frequency signal;

sensor means responsive to the motor for producing angular positionsignals and including an output signal having a frequency in accordancewith the speed of the motor;

phase comparator means for comparing the reference frequency signal withthe sensor output signal and for producing an output pulse train inwhich each pulse thereof is determined in accordance with the differencein frequency and phase between the reference frequency signal and thesen sor output signal;

integrator-digital-to-analog converter means for converting the outputof said phase comparator into an analog error signal voltage, biasingmeans for converting said analog error signal voltage to abi-directional error signal voltages; and means responsive to thebi-directional error signal voltage of said biasing means forcontrolling aceel eration or deceleration of said motor to achievesymmetrical bi-directional torque control thereof.

2. A combination as claimed in claim 1, wherein the last mentioned meansincludes an absolute value amplifier coupled to receive saidbi-directional error signal voltage for producing an pair of amplitudecontrol signals; and rotational decoder means connected to said absolutevalue amplifier for cooperating therewith to produce a polarity controlsignal.

3. A combination as claimed in claim 2, wherein the said last mentionedmeans further comprises position decoder means. connected to receivesaid angular position signals from said sensor means and said polaritycontrol signal from said rotational decoder means, for producing anelectrical signal in accordance with the position of the output shaft; apair of amplifier means connected to receive respective ones of the pairof amplitude control signals of said absolute value amplifier and theoutput of said position decoder means; and switching means responsive tothe output of said am plifier means for controlling the sequence andlevel of current flow through the motor windings.

4. A combination as claimed in claim 3, wherein said pair of amplifiermeans each comprise an operational amplifier having a first inputconnected to a respective one of the amplitude control signals of saidabsolute value amplifier; power commutator means connected to the outputof said operational amplifier and to the output of said position decodermeans; and a current feedback loop connected between said power commatator means and a second input to said operational amplifier.

5. A combination as claimed in claim 4, wherein said position decodermeans includes a pair of position decoders, each having a first inputconnected to receive a respective angular position signal from saidsensor means and a second input connected to receive the polaritycontrol signal from said rotation decoder means, the outputs thereofbeing coupled to the powercommutator of respective ones of said pair ofamplifier means.

6. A combination as claimed in claim 1, further comprising overspeedcontrol means resposive to the output signal of said sensor means andsaid reference frequency signal and having an output combined with saidbi-direction error signal for preventing the speed of said motor fromexceeding a predetermined value.

7. A combination as claimed in claim l, wherein said sensor meansincludes position sensor means for sensing the absolute position of theoutput shaft of said motor for motor commutation purposes and encodermeans for producing said output signal having a frequency in accordancewith the speed of said motor.

1. In combination, a brushless D.C. motor and motor speed control systemfor controlling the speed of said motor, said system comprising: meansfor generating a reference frequency signal; sensor means responsive tothe motor for producing angular position signals and including an outputsignal having a frequency in accordance with the speed of the motor;phase comparator means for comparing the reference frequency signal withthe sensor output signal and for producing an output pulse train inwhich each pulse thereof is determined in accordance with the differencein frequency and phase between the reference frequency signal and thesensor output signal; integrator-digital-to-analog converter means forconverting the output of said phase comparator into an analog errorsignal voltage, biasing means for converting said analog error signalvoltage to a bi-directional error signal voltages; and means responsiveto the bi-directional error signal voltage of said biasing means forcontrolling acceleration or deceleration of said motor to achievesymmetrical bi-directional torque control thereof.
 2. A combination asclaimed in claim 1, wherein the last mentioned means includes anabsolute value amplifier coupled to receive said bi-directional errorsignal voltage for producing an pair of amplitude control signals; androtational decoder means connected to said absolute value amplifier forcooperating therewith to produce a polarity control signal.
 3. Acombination as claimed in claim 2, wherein the said last mentioned meansfurther comprises position decoder means, connected to receive saidangular position signals from said sensor means and said polaritycontrol signal from said rotational decoder means, for producing anelectrical signal in accordance with the position of the output shaft; apair of amplifier means connected to receive respective ones of the pairof amplitude control signals of said absolute value amplifier and theoutput of said position decoder means; and switching means responsive tothe output of said amplifier means for controlling the sequence andlevel of current flow through the motor windings.
 4. A combination asclaimed in claim 3, wherein said pair of amplifier means each comprisean operational amplifier having a first input connected to a respectiveone of the amplitude control signals of said absolute value amplifier;power commutator means connected to the output of said operationalamplifier and to the output of said position decoder means; and acurrent feedback loop connected between said power commutator means anda second input to said operational amplifier.
 5. A combination asclaimed in claim 4, wherein said position decoder means includes a pairof position decoders, each having a first input connected to receive arespective angular position signal from said sensor means and a secondinput connected to receive the polarity control signal from saidrotation decoder means, the outputs thereof being coupled to the powercommutator of respective ones of said pair of amplifier means.
 6. Acombination as claimed in claim 1, further comprising overspeed controlmeans resposive to the output signal of said sensor means and saidreference frequency signal and having an output combined with saidbi-direction error signal for preventing the speed of said motor fromexceeding a predetermined value.
 7. A combination As claimed in claim 1,wherein said sensor means includes position sensor means for sensing theabsolute position of the output shaft of said motor for motorcommutation purposes and encoder means for producing said output signalhaving a frequency in accordance with the speed of said motor.